I’m not an FPGA expert, but I dabble.
I asked some folks (much smarter than I) to run some back-of-envelope calculations for my preferred Xilinx Spartan-3E. It has 1200k gates, runs at 50 Mhz, and so on. You can get into it for $150 or so. (Digilent Nexys2 is hard to beat)
The upshot was that a modern desktop machine has such a huge clockspeed advantage (8 cores at 3 GHz?), so only a massively parallel implementation would have a chance of competing. There really isn’t much of an I/O constraint, so it’s just grinding on the nonce and testing for success. Most of the commercial SHA256 cores focus on I/O bandwidth, for the typical application of passing a lot of data into the hash. This is something much different, with self-generated inputs and a test on the output of each cycle.
So.. How many rounds can you fit in a million gates?
A modern GPU and some crafty OpenCL/CUDA code seems like a better avenue for research, rapid turnaround, and scalable speeds. You’d have both high clock speeds and parallelism at work.